Product Description
The S001F24A39 integrated pyroelectric flame sensor utilizes a new environmentally friendly lithium
tantalate (LiTaO) single-crystal material for its sensing element. It is a 4-pin digital PIR flame sensor
that integrates a digital signal conditioning chip (IC) with the sensing element within an electromagnetic
shielding cover. The probe communicates bidirectionally with an external controller to configure various
operational states. The sensing element couples the detected flame flicker signal into the digital signal
conditioning IC through a very high-impedance differential input circuit. The digital IC chip converts
the signal into a digital format via a 14-bit ADC, facilitating subsequent signal processing and logic
control.Configurations such as detection sensitivity (trigger threshold), blind time after trigger reset, signal pulse counting time window, algorithms, and the selection of three operating modes can be implemented by the external controller (µC) through the single-wire communication interface (SERIN) to configure internal registers. During routine continuous flame sensing, the µC does not need to remain active (it can enter standby mode to save power). Only when the digital probe detects a flame flicker signal meeting the pre-configured trigger conditions does the internal conditioning IC send an interrupt wake-up command to the µC via the INT/DOCI interface, prompting the µC to activate and execute subsequent control actions. Depending on the configured operating mode, the µC can also periodically or forcibly read the digital flame signal value from the probe through the DOCI port, and then determine follow-up actions based on its programmed algorithm.Thanks to the power-efficient interrupt wake-up mechanism, this digital sensing system is ideal for applications with high energy-saving requirements, particularly battery-powered scenarios, making it the most energy-efficient sensing control solution available.
2.Characteristic
1.Digital signal processing with bidirectional communication to the controller;
2.Configurable detection trigger conditions and support for three different operating modes, enabling open flame monitoring results output and ADC-filtered flame signal data output;
3.Built-in second-order Butterworth bandpass filter for the infrared sensor, shielding input interference from other frequencies;
4.The infrared signal conditioning circuit is fully encapsulated within an electromagnetic shielding cover, with only power and digital interface pins exposed, providing exceptional resistance to radio frequency interference;
5.The system's operational mechanism is deeply optimized for power efficiency, making it suitable for battery-powered devices;
6.Power supply voltage and on-chip temperature detection;
7.Operates with quick stabilization after a self-check during power-up;
8.Utilizes eco-friendly LiTaO sensing material, strictly complying with RoHS environmental requirements without the need for exemptions or RoHS certification.
3.Application
1. Various open flame monitors;
2. Fire detectors;
3. Internet of Things flame sensing equipment;
4. Fire alarms for homes, industrial plants, and factories.
Product Parameters
4. Performance parameters
4.1 Maximum Ratings
Electrical overstress exceeding the parameters in the table below may cause permanent damage to the device. Operation beyond the maximum rated conditions may affect the reliability of the device.
Parameter |
Symbol |
Min. |
Max. |
Unit |
|
Supply voltage |
VDD |
-0.3 |
3.6 |
V |
25ºC |
Pin voltage |
Vnto |
-0.3 |
Vdd + 0.3 |
V |
25ºC |
Pin current |
Into |
-100 |
100 |
mA |
Single time ,single pin |
Storage temperature |
TST |
-30 |
70 |
ºC |
< 60% R.H |
Operating temperature |
Toper |
-20 |
55 |
ºC |
|
4.2 Electrical Characteristics (Typical test conditions: TAMB=+25ºC, VDD=+3V)
Parameter |
Symbol |
Min. |
Typical |
Max. |
Unit |
Note |
Working conditions |
Operating voltage |
VDD |
1.5 |
3 |
3.6 |
V |
|
Working current, Vreg on |
IDD1 |
|
5 |
6.0 |
µA |
This product is not suitable |
Operating current, Vreg off |
IDD |
|
3 |
3.5 |
µA |
Applicable to this product Vdd = 3V, no load |
Input parameters SERIN |
Input low voltage |
VIL |
- 0.3 |
|
0.2Vdd |
V |
|
Input high voltage |
VIH |
0.8Vdd |
|
0.3 + Vdd |
V |
Max V < 3.6V |
Input current |
Ii |
-1 |
|
1 |
µA |
Vss<Vin<Vdd |
Digital clock low level time |
tL |
200 |
|
0.1/ FCLK |
nS/µS |
Typical: 1-2µS |
Digital clock high level time |
tH |
200 |
|
0.1/ FCLK |
nS/µS |
Typical: 1-2µS |
Data bit writing time |
tBW |
2/FCLK - tH |
|
3/FCLK-- tH |
µS |
Typical: 80-90µS |
Write timeout |
tWA |
16/FCLK |
|
17/FCLK |
µS |
|
Output pin INT/DOCI-OUT |
Input low voltage |
VIL |
- 0.3 |
|
0.2Vdd |
V |
|
Input high voltage |
VIH |
0.8Vdd |
|
0.3 + Vdd |
V |
Max V < 3.6V |
Input current |
IDI |
-1 |
|
1 |
µA |
Vss<Vin<Vdd |
Data readable setup time |
TDS |
4/Fclk |
|
5/Fclk |
µS |
|
Data bit preparation time |
TBs |
|
|
1 |
µS |
CLOAD < 10pF |
Forced reading settling time |
TFR |
4/FCLK |
|
|
µS |
|
Interrupt clear time |
TCL |
4/FCLK |
|
|
µS |
|
Digital clock low level time |
TL |
200 |
|
0.1/ FCLK |
nS/µS |
Typical: 1-2µS |
Digital clock high level time |
TH |
200 |
|
0.1/ FCLK |
nS/µS |
Typical: 1-2µS |
Bit data read time |
Tbit |
|
|
24 |
µS |
Typical: 20-22µS |
Reading timeout |
TRA |
4/FCLK |
|
|
µS |
|
DOCI pull-down duration |
TDU |
32/FCLK |
|
|
µS |
For data update |
Input PIRIN/NPIRIN |
PIRIN/NPIRIN to Vss Input Impedance |
|
30 |
|
60 |
GΩ |
-60mV<Vin<60mV |
Input resistance differential value |
|
60 |
|
120 |
GΩ |
-60mV<Vin<60mV |
PIRIN Input voltage range |
|
-53 |
|
+53 |
mV |
|
Resolution/step size |
|
6 |
6.5 |
7 |
µV/Count |
|
ADC output range |
|
511 |
|
2^14-511 |
Counts |
|
ADC Bias |
|
7150 |
8130 |
9150 |
Counts |
|
ADC Temperature Coefficient |
|
-600 |
|
600 |
ppm/K |
|
ADC Input noise RMS valueF = 0.1Hz...10Hz |
|
|
39 |
91 |
µVpp |
f = 0.09...7Hz |
Supply voltage measurement |
ADC Output range |
|
2^13 |
|
2^14-511 |
Counts |
|
Voltage resolution |
|
590 |
650 |
720 |
µV/Count |
|
ADC Bias @ 3V |
|
|
12600 |
|
Counts |
about ±10% offset |
Temperature measurement (single point calibration required) |
Resolution |
|
|
80 |
|
Counts/K |
|
ADC output range |
|
511 |
|
2^14-511 |
Counts |
|
Bias value @ 298K |
|
|
8130 |
|
Counts |
about ±10% offset |
Oscillators and filters |
Low pass filter cutoff frequency |
|
FCLK*1.41/2048/π |
Hz |
2nd order BW |
High pass filter cutoff frequency |
|
FCLK*P*1.41/32768/π |
Hz |
2nd order BW P = 1 or 0.5 |
On-chip oscillator frequency |
Fosci |
60 |
64 |
72 |
kHz |
|
System clock |
FCLK |
|
Fosci/2 |
|
kHz |
|
4.4 Test Method
|
1: Blackbody 500K 2: 1Hz chopper 3: Grating Ø4mm 4: Baffle 5: PIR 6: Digital signal
|
Parameter |
Symbol |
Typical |
Min. |
Max. |
Unit |
Note |
Sensitivity |
Vp-p |
200 |
160 |
|
uV |
|
noise |
Vp-p |
26 |
|
39 |
uV |
|
4.6 Output trigger or alarm event logic
The output signal of the bandpass or lowpass (depending on the configuration) filter is calculated. When the flame signal value level exceeds the pre-configured sensitivity threshold, an internal pulse is generated. When the signal changes sign (or does not need to change sign) and exceeds the set threshold again, a second pulse is calculated. The conditions for output triggering or fire alarm, such as the number of pulses and the counting time window in which the pulse occurs, are configurable. If the previous event is cleared by resetting the interrupt, the detection stops for the next configurable blind lock time. This feature is very important to prevent self-excited false triggering in application scenarios that require high sensitivity to detect fire alarms.
The interrupt will be cleared by driving a low level "0" for at least 120µs (tCL); the processor can then switch the port back to a high impedance state.
4.7 Serial interface and configurable register function description
The configuration of the conditioning IC control algorithm is achieved by programming the conditioning IC related registers through the SERIN pin of the controller, using a simple clock data single-wire communication protocol. The configured data of the conditioning IC is read out by the controller using the INT/DOCI pin, using a similar clock data single-wire output protocol. When SERIN is at a low level for at least 16 system clocks (and Vdd is in the normal range), the conditioning IC inside the probe begins to accept new data.
The following parameters can be configured and adjusted through the conditioning IC registers:
Window lens size, transmission spectrum and viewing angle
Central wavelength(nm) |
Half-peak width (nm) |
Peak transmittance |
Cut-off range (nm) |
3910±40 |
90±20 |
≥75% |
UV~11000(≤1%) |
Optical size:
|
numeric value |
Unit |
window size |
5.2*4.2 |
mm2 |
Sensitive element area |
2*1.5 |
mm2 |
Transmittable center wavelength |
3.87-3.95 |
μm |
Detection Angle |
100 |
Deg. |
Detailed Photos
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